AOI_4_unit

module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule

module test;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #50 clock1(x_in1);
system_clock #50 clock2(x_in2);
system_clock #20 clock3(x_in3);
system_clock #20 clock4(x_in4);

AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

------------------------------------------------------

Add-half

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
Add_half AH1(sum,c_out,a,b);
endmodule

module Add_half(sum,c_out, a, b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial clk = 0;
always begin#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
endalways@(posedge clk)if($time > 1000) #(PERIOD-1)$stop;
endmodule

Add_full

由2個半加法器與1個OR閘所組成

module Add_full(a,b,c_in,sum,c_out);
intput a,b,c_in;
output sum,c_out;
wire w1,w2,w3
add_half M1(w1,w2,a,b);
add_half M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule
---------------------------------------------

Test Add-half

module add-half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar; // 內部接線
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
------------------------------------------
Behavioral model 行為模式
always

begin

sum = a + b;
c = a & b;

end

verilog test(一)

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a & b;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
end

always @ (posedge clk)
if($time>1000) #(PERIOD-1)$stop;
endmodule