Behaviornl Model

module D_filp_flop(q,data_in,clk)
input data_in,clk;
output q;
reg q;
always@(clk)
begin
if(clk==0)
q=q;
else
q=data_in;
end
endmodule

上課的

2.5 Glitches and Hazards

The output of a combinational circuit make a transition even though the logical
values applied at its inputs do not imply a change.

These unwated switching transients called "glitches"

(●_●)?

module conmpare_2_b(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B({A1,A0} < {B1,B0});
assign A_gt_B({A1,A0} < {B1,B0});
assign A_eq_B({A1,A0} == {B1,B0});

endmodule

module conmpare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output [1:0] A,B;
reg A_lt_B,A_gt_B,A_eq_B;
always @(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

2-bit 比較器

module conmpare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or(A_lt_B,w1,w2,w3);
nor(A_gt_B,A_lt_B,A_eq_B);
and(A_eq_B,w4,w5);
and(w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,A0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);
endmodule

AOI_4_unit

module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule

module test;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #50 clock1(x_in1);
system_clock #50 clock2(x_in2);
system_clock #20 clock3(x_in3);
system_clock #20 clock4(x_in4);

AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

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Add-half

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
Add_half AH1(sum,c_out,a,b);
endmodule

module Add_half(sum,c_out, a, b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial clk = 0;
always begin#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
endalways@(posedge clk)if($time > 1000) #(PERIOD-1)$stop;
endmodule

Add_full

由2個半加法器與1個OR閘所組成

module Add_full(a,b,c_in,sum,c_out);
intput a,b,c_in;
output sum,c_out;
wire w1,w2,w3
add_half M1(w1,w2,a,b);
add_half M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule
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