(●_●)?

module conmpare_2_b(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B({A1,A0} < {B1,B0});
assign A_gt_B({A1,A0} < {B1,B0});
assign A_eq_B({A1,A0} == {B1,B0});

endmodule

module conmpare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output [1:0] A,B;
reg A_lt_B,A_gt_B,A_eq_B;
always @(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule