上課的

2.5 Glitches and Hazards

The output of a combinational circuit make a transition even though the logical
values applied at its inputs do not imply a change.

These unwated switching transients called "glitches"

(●_●)?

module conmpare_2_b(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;

assign A_lt_B({A1,A0} < {B1,B0});
assign A_gt_B({A1,A0} < {B1,B0});
assign A_eq_B({A1,A0} == {B1,B0});

endmodule

module conmpare_2_algo(A_lt_B,A_gt_B,A_eq_B,A,B);
input [1:0] A,B;
output [1:0] A,B;
reg A_lt_B,A_gt_B,A_eq_B;
always @(A or B)
begin
A_lt_B=0;
A_gt_B=0;
A_eq_B=0;
if(A==B) A_eq_B=1;
else if(A>B) A_gt_B=1;
else A_lt_B=1;
end
endmodule

2-bit 比較器

module conmpare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or(A_lt_B,w1,w2,w3);
nor(A_gt_B,A_lt_B,A_eq_B);
and(A_eq_B,w4,w5);
and(w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,A0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);
endmodule