verilog test(一)

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a & b;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial
clk=0;
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
end

always @ (posedge clk)
if($time>1000) #(PERIOD-1)$stop;
endmodule